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4 MEG x 16 EDO DRAM
DRAM
FEATURES
* Single +3.3V 0.3V power supply * Industry-standard x16 pinout, timing, functions, and package * 12 row, 10 column addresses (R6) 13 row, 9 column addresses (N3) * High-performance CMOS silicon-gate process * All inputs, outputs and clocks are LVTTL-compatible * Extended Data-Out (EDO) PAGE MODE access * 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms * Optional self refresh (S) for low-power data retention
MT4LC4M16R6, MT4LC4M16N3
For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View) 50-Pin TSOP
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC
A12
OPTIONS
* Plastic Package 50-pin TSOP (400 mil) * Timing 50ns access 60ns access * Refresh Rates 4K 8K Standard Refresh Self Refresh * Operating Temperature Range Commercial (0C to +70C) Extended (-40C to +85C)
MARKING
TG
-5 -6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC/A12 A11 A10 A9 A8 A7 A6 VSS
R6 N3 None S*
for N3 version, NC for R6 version.
MT4LC4M16R6 Configuration Refresh Row Address Column Addressing 4 Meg x 16 4K 4K (A0-A11) 1K (A0-A9)
MT4LC4M16N3 4 Meg x 16 8K 8K (A0-A12) 512 (A0-A8)
None IT**
NOTE: 1. The "#" symbol indicates signal is active LOW. *Contact factory for availability. **Available only on MT4LC4M16R6 standard refresh device.
Part Number Example:
4 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER MT4LC4M16R6TG-x MT4LC4M16R6TG-x S MT4LC4M16N3TG-x MT4LC4M16N3TG-x S x = speed REFRESH ADDRESSING PACKAGE REFRESH 4K 4K 8K 8K 400-TSOP Standard 400-TSOP Self 400-TSOP Standard 400-TSOP Self
MT4LC4M16R6TG-5
KEY TIMING PARAMETERS
SPEED -5 -6
tRC 84ns 104ns tRAC
50ns 60ns
tPC 20ns 25ns
tAA 25ns 30ns
tCAC
tCAS
13ns 15ns
8ns 10ns
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
FUNCTIONAL BLOCK DIAGRAM MT4LC4M16R6 (12 row addresses)
WE#
CASL# CASH#
CAS# DATA-IN BUFFER
16
DQ0DQ15
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
16
OE#
16
10
COLUMNADDRESS BUFFER(10) REFRESH CONTROLLER
16
10
COLUMN DECODER
1,024
SENSE AMPLIFIERS I/O GATING
1,024 x 16
A0A11
REFRESH COUNTER
ROW SELECT
12 12 ROWADDRESS BUFFERS (12)
ROW DECODER
COMPLEMENT SELECT
12
4,096
4,096 x 16
4,096 x 1,024 x 16 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
VDD VSS
FUNCTIONAL BLOCK DIAGRAM MT4LC4M16N3 (13 row addresses)
WE#
CASL# CASH#
CAS# DATA-IN BUFFER
16
DQ0DQ15
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
16
OE#
16
9
COLUMNADDRESS BUFFER(9) REFRESH CONTROLLER
16
9
COLUMN DECODER
512
SENSE AMPLIFIERS I/O GATING
512 x 16
A0A12
REFRESH COUNTER
ROW SELECT
13 13 ROWADDRESS BUFFERS (13)
COMPLEMENT SELECT
ROW DECODER
13
8192
8192 x 16
8192 x 512 x 16 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
Vcc Vss
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MT4LC4M16R6 or 8,192 rows by 512 columns on the MT4LC4M16N3. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 column-address bits (A0-A9) on the MT4LC4M16R6 or 13 row-address bits (A0-A12) and 9 column-address bits (A0-A8) on the MT4LC4M16N3 version. In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) is such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data is such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the RAS# signal, then the column address is latched by CAS#. This device provides EDO-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE or READMODIFY-WRITE) within a given row. The 4 Meg x 16 DRAM must be refreshed periodically in order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Using only one of the two signals results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for
WORD WRITE RAS#
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE (DQ0-DQ7) OF WORD
STORED DATA 1 1 0 1 1 1 1 1
INPUT DATA 0 0 1 0 0 0 0 0
INPUT DATA
STORED DATA 0 0 1 0 0 0 0 0
STORED DATA 0 0 1 0 0 0 0 0
INPUT DATA 1 1 0 1 1 1 1 1
INPUT DATA
STORED DATA 1 1 0 1 1 1 1 1
UPPER BYTE (DQ8-DQ15) OF WORD
0 1 0 1 0 0 0 0
X X X X X X X X ADDRESS 0
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
X X X X X X X X ADDRESS 1
1 0 1 0 1 1 1 1
X = NOT EFFECTIVE (DON'T CARE)
Figure 1 WORD and BYTE WRITE Example
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
DRAM ACCESS (continued)
the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READMODIFY-WRITE occurs when WE falls after CAS# (CASL# or CASH#) is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 64Mb EDO DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are
WORD READ RAS#
LOWER BYTE READ
CASL#
CASH#
WE#
LOWER BYTE (DQ0-DQ7) OF WORD
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
UPPER BYTE (DQ8-DQ15) OF WORD
ADDRESS 0 Z = High-Z
ADDRESS 1
Figure 2 WORD and BYTE READ Example
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
RAS# V IH V IL
CAS#
V IH V IL
ADDR
V IH V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH V IOL
OPEN
VALID DATA (A) tOD tOES
VALID DATA (A)
VALID DATA (B) tOD tOEHC
VALID DATA (C) tOD
VALID DATA (D)
OE#
V IH V IL
tOE tOEP
The DQs go back to Low-Z if tOES is met.
The DQs remain High-Z until the next CAS# cycle if tOEHC is met.
The DQs remain High-Z until the next CAS# cycle if tOEP is met.
Figure 3 OE# Control of DQs
RAS#
V IH V IL
CAS#
V IH V IL
ADDR
V IH V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH V IOL
OPEN
VALID DATA (A) tWHZ
VALID DATA (B) tWHZ
INPUT DATA (C)
WE#
V IH V IL V IH V IL
tWPZ
OE#
The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). DON'T CARE UNDEFINED
Figure 4 WE# Control of DQs
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EDO PAGE MODE (continued)
two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and keep OE# HIGH for tOEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again. The second method is to have OE# LOW when CAS# transitions HIGH and then bring OE# HIGH for a minimum of tOEP anytime during the CAS# HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again (see Figure 3). During other cycles, the outputs are disabled at tOFF time after RAS# and CAS# are HIGH or at tWHZ after WE# transitions LOW. The tOFF time is referenced from the rising edge of RAS# or CAS#, whichever occurs last. WE# can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 4. EDO-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the EDO-PAGE-MODE operation. rows for N3 or 4,096 rows for R6). The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16N3 internally refreshes two rows for each CBR cycle, whereas the MT4LC4M16R6 refreshes one row for every CBR cycle. For either device, executing 4,096 CBR cycles will refresh the entire device. The CBR REFRESH will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method, only one row is refreshed on each cycle. Thus, 8,192 RAS-only REFRESH cycles are needed every 64ms on the MT4LC4M16N3 in order to refresh the entire device. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the "S" version. The self refresh feature is initiated by performing a CBR Refresh cycle and holding RAS# low for the specified tRASS. The "S" option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25s per cycle, when using a distributed CBR refresh. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh, however, if the controller is using RAS# only or burst CBR refresh then a burst refresh using tRC (MIN) is required.
DRAM REFRESH
The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the 4 Meg x 16 DRAM array at least once every 64ms (8,192
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) Commercial ......................................... 0C to +70C Extended (IT) ................................. -40C to +85C** Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ................................................... 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Available only on MT4LC4M16R6 standard refresh device.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (VCC = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN (0V VIN VCC + 0.3V); All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA OUTPUT LOW VOLTAGE: IOUT = 2mA OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V VOUT VCC + 0.3V); DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II MIN 3 2 -0.3 -2 MAX 3.6 VCC + 0.3 0.8 2 UNITS NOTES V V V A 35 35 36
VOH VOL IOZ
2.4 - -5
- 0.4 5
V V A
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4 MEG x 16 EDO DRAM
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V 0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# VCC - 0.2V; DQs may be left open; Other inputs: VIN VCC - 0.2V or VIN 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended ("S" version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A10, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open); tRC = 125s REFRESH CURRENT: Self ("S" version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A10, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) SYMBOL SPEED ICC1 ALL MAX 4K 1 8K 1 UNITS NOTES mA
ICC2 ICC3
ALL -5 -6 -5 -6 -5 -6 -5 -6 ALL
500 150 165 120 125 150 165 150 165 400
500 115 130 120 125 115 130 150 165 400
A mA 26
ICC4
mA
26
ICC5
mA
22
ICC6
mA
4, 7, 23 4, 7, 23, 37
ICC7
A
ICC8
ALL
350
350
A
4, 7, 37
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
CAPACITANCE
(Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 5 7 7 UNITS pF pF pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to "Don't Care" during Self Refresh CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOEHC tOEP tOES tOFF tORD
-6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 15 10 5 0 3 10 5 45 5 35 10 10 0 0 10 10 5 5 0 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 12 38 0 0 42 8 8 15 8 5 0 3 8 5 38 5 28 8 8 0 0 8 5 5 4 0 0
10,000
28 28 18 29 28 30, 32 4, 31 31 29 13, 33 29 31 31 4, 28 18, 28 31 19, 29 19, 29 24, 25 20 25
28
35
12 12
15 15
12
15
17, 24, 29
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4 MEG x 16 EDO DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period Refresh period ("S" version) RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse widths to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 20 47 9 7 50 50 100 84 11 0 0 MAX MIN 25 56 12 10 60 60 100 104 14 0 0 -6 MAX UNITS ns ns ns ns ns ns ns s ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 34 34 15
50
60
10,000 125,000
10,000 125,000
64 128 30 5 90 0 13 116 67 13 2 8 38 0 5 10 8 8 40 5 105 0 15 140 79 15 2 10 45 0 5 10 10 10
64 128
14, 28 16, 30 28 22, 23 23
16 35 18
50
50
35 18, 28
12
15
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
NOTES
1. 2. 3. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V; f = 1 MHz; TA = 25C. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100s is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 2.5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# and RAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates and 100pF; and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD, and tCWD define READMODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW results in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 22. RAS#-ONLY REFRESH requires that all 8,192 rows of the MT4LC4M16N3 or all 4,096 rows of the MT4LC4M16R6 be refreshed at least once every 64ms. 23. CBR REFRESH for either device requires that at least 4,096 cycles be completed every 64ms. 24. The DQs go High-Z during READ cycles once tOD or tOFF occur. If CAS# stays LOW while OE# is brought HIGH, the DQs will go High-Z. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 25. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 26. Column address changed once each cycle. 27. The first CASx# edge to transition LOW.
4. 5.
6.
7. 8.
9.
10. 11. 12. 13.
14.
15.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
NOTES (continued)
28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Each CASx# must meet minimum pulse width. 30. The last CASx# edge to transition HIGH. 31. Last falling CASx# edge to first rising CASx# edge. 32. Last rising CASx# edge to first falling CASx# edge. 33. Last rising CASx# edge to next cycle's last rising CASx# edge. 34. Last CASx# to go LOW. 35. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 36. NC pins are assumed to be left floating and are not tested for leakage. 37. Self refresh and extended refresh for either device requires that at least 4,096 cycles be completed every 128ms.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP CAS# V IH V IL tAR tASR tRAD tRAH tASC tACH V IH V IL tCAH tRCD tCAS tRRH tRP
RAS#
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ tOFF
NOTE 1
DQ
V OH V OL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 5 0 5 12 45 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF
tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 9 7 50 84 11 0 0 30 0 13 10,000 MAX 12 12 50 12 10 60 104 14 0 0 40 0 15 MIN 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 5 0 5 38 0
10,000
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tACH ROW tCWL tRWL tWCS tWCR tWCH tWP WE# V IH V IL tDS V DQ V IOH IOL V IH V IL tDH tRCD tCAS tRP
RAS#
ROW
COLUMN
VALID DATA
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tACH tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS
-6 MAX MIN 15 45 0 0 10 10,000 10 5 5 45 10 10 0 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD tRAH
tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 9 7 50 84 11 30 13 13 8 38 0 5 MAX MIN 12 10 60 104 14 40 15 15 10 45 0 5
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 5 5 38 8 8 0
10,000
10,000
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
tCRP V IH V IL tAR tRAD tRAH
tRCD
CAS#
tASR ADDR V IH V IL
tASC
tCAH
tACH ROW
ROW
COLUMN tRWD tCWD tAWD tCWL tRWL tWP
tRCS
WE#
V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH
V DQ V IOH IOL
OPEN
VALID D IN tOEH
OPEN
OE#
DON' T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL tDH
-6 MAX 25 MIN 15 45 0 0 49 13 15 10 10,000 10 5 0 5 45 35 10 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tDS tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-5 MIN 0 0 8 50 9 7 50 11 0 30 13 116 67 13 5 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 0 10
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 42 8 8 5 0 5 38 28 8 8
10,000
10,000
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EDO-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP CAS# V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tACH tASC tCAH tACH tASC tACH tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
ROW tRCS
COLUMN
COLUMN
COLUMN tRCH tRRH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ tAA tCPA tCAC tCOH VALID DATA tOE VALID DATA tOD tCLZ tOEHC
tAA tCPA tCAC
tOFF
DQ
V OH V OL
OPEN
VALID DATA tOE tOES tOEP tOD
OPEN
OE#
V IH V IL
tOES
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tOD
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 5 0 3 10 28 35 5 12 45 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE
tOEHC tOEP tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 5 5 4 0 20 9 7 50 11 0 0 30 0 13 125,000 12 50 12 10 60 14 0 0 40 0 15 MAX 12 MIN 10 5 5 0 25
-6 MAX 15 UNITS ns ns ns ns 15 60 ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 5 0 3 8 5 38 0
125,000
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EDO-PAGE-MODE EARLY WRITE CYCLE
t RASP V IH V IL t CSH t CRP V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC tACH t CAH t ASC t ACH t CAH t ASC t ACH t CAH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CP t RP
RAS#
CAS#
ROW
COLUMN t CWL t WCS t WCH t WP
COLUMN t CWL t WCS t WCH t WP
COLUMN t CWL t WCS t WCH t WP
ROW
WE#
V IH V IL t WCR t DS t DH t DS t DH t DS t RWL t DH
V DQ V IOH IOL
VALID DATA
VALID DATA
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tACH tAR tASC tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS
-6 MAX MIN 15 45 0 0 10,000 10 10 5 10 5 45 10 10 0 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tPC tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 20 9 7 50 11 30 13 13 8 38 0 5 125,000 MAX MIN 25 12 10 60 14 40 15 15 10 45 0 5
-6 MAX UNITS ns ns ns 125,000 ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 5 8 5 38 8 8 0
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tRAH tRCD tCAS tCP tPC tPRWC NOTE 1 tCAS tCP tRSH tCAS tCP tRP
RAS#
tASR ADDR V IH V IL
tASC
tCAH
tASC
tCAH
tASC
tCAH
ROW
COLUMN tRWD tRCS tCWL tWP tAWD tCWD
COLUMN
COLUMN tRWL tCWL tAWD tCWD tWP
ROW
tCWL tWP tAWD tCWD
WE#
V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD tOE tOE VALID VALID D OUT D IN tOD tOE tDH tDS tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD tOEH OPEN tDH tDS
DQ
V IOH V IOL
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH
-6 MAX 25 MIN 45 0 0 49 13 15 10 10 5 0 10 28 35 5 45 35 10 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tOD
tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-5 MIN 0 0 8 20 47 50 9 7 50 11 0 30 13 67 13 5 125,000 12 10 60 14 0 40 15 79 15 5 MAX 12 12 10 25 56 MIN 0 0
-6 MAX 15 15 UNITS ns ns ns ns ns ns 60 ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 5 0 8 5 38 28 8 8
10,000
125,000
NOTE: 1. tPC is for LATE WRITE cycles only.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP RAS# V IH V IL t CSH tPC tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH ROW tASC tCAH t ASC t CAH tASC t ACH t CAH t RCD t CAS t CP t CAS tPC t CP t CAS tRSH t CP t RP
COLUMN (A) tRCS
COLUMN (B) tRCH
COLUMN (N) tWCS tWCH
ROW
WE#
V IH V IL tRAC
tAA tCPA tCAC
tAA
tCAC tCOH t WHZ VALID DATA (B)
t DS
t DH
DQ V IOH V IOL V IH V IL
OPEN tOE
VALID DATA (A)
VALID DATA IN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 3 10 5 45 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ
-5 MIN 20 50 9 7 50 11 0 0 30 13 8 0 12 125,000 12 10 60 14 0 0 40 15 10 0 MAX 12 25 MIN
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns 15 ns ns
MIN 12 38 0 0 8 8 3 8 5 38 8 0
125,000
28
35
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
READ CYCLE (with WE#-controlled disable)
RAS# V IH V IL tCSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tASC tRCD tCAS tCP
CASL#/CASH#
ADDR
ROW tRCS
COLUMN tRCH tWPZ tRCS
COLUMN
WE#
V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ
V DQ V OH OL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH
-6 MAX 25 MIN 45 0 0 13 15 10 10,000 10 0 10 5 45 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ
-5 MIN 0 MAX 12 12 50 9 7 11 0 0 12 10 10 12 10 14 0 0 MIN 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns 15 ns ns
MIN 38 0 0 8 8 0 8 5 38
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON'T CARE)
tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP
RAS#
CASL#/CASH#
ROW
ROW
V Q V OH OL
OPEN
CBR REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CASL#/CASH# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS
DQ
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tASR tCHR tCP tCRP tCSR tRAH
-6 MAX MIN 0 10 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC
tRP tRPC tWRH tWRP
-5 MIN 50 84 30 5 8 8 MAX 10,000 MIN 60 104 40 5 10 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 8 8 5 5 7
NOTE: 1. End of first CBR REFRESH cycle.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW)
tRC tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS
CASL#/CASH#
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ tOFF
DQx
V IOH V IOL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
tORD
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR
tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 12 5 0 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF
tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH
-5 MIN 0 0 50 9 7 50 11 30 13 10,000 12 10 60 14 40 15 MAX 12 12 MIN 0 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 5 0
10,000
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
SELF REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2
RAS#
tRPC tCP
tRPC tCP
(( ))
CASL#/ CASH#
V IH V IL V OH V OL V IH V IL
DQ
WE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tCHD tCLCH tCP tCSR tRASS MIN 15 5 8 5 100 MAX MIN 15 5 10 5 100 -6 MAX UNITS ns ns ns ns ns SYMBOL tRP tRPC tRPS tWRH tWRP MIN 30 5 90 8 8 -5 MAX MIN 40 5 105 10 10 -6 MAX UNITS ns ns ns ns ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
23
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 EDO DRAM
50-PIN PLASTIC TSOP (400 mil)
21.04 20.88 .88 TYP 50
11.86 11.66
10.21 10.11
SEE DETAIL A
1 .80 TYP
25 .45 .30 .18 .13
PIN #1 ID
.25 GAGE PLANE .10 1.2 MAX
.20 .25
.60 .40
DETAIL A
.80 TYP
NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
4 Meg x 16 EDO DRAM D29_2.p65 - Rev. 5/00
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.

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